`include "define.svh"

module inst_sram_like_interface(
    // from IF-stage
    input wire                          inst_sram_en,
    input wire [`REG_WIDTH - 1 : 0]     inst_sram_addr,
    // Master to slave outputs
    output reg                          inst_req,
    output reg                          inst_wr,
    output reg [1 : 0]                  inst_size,
    output reg [`PC_WIDTH - 1 : 0]      inst_addr,
    output reg [3 : 0]                  inst_wstrb,
    output reg [`REG_WIDTH - 1 : 0]     inst_wdata,
    // Slave to master inputs
    input wire                          inst_addr_ok_i,
    input wire                          inst_data_ok_i,
    // To IF/ID-stages
    output reg                          inst_addr_ok_o,
    output reg                          inst_data_ok_o
    // inst_rdata send to ID-stage directly
);

    always_comb inst_wr = 0;                 // read request
    always_comb inst_size = 2'b10;           // read 4 bytes
    always_comb inst_wstrb = 4'b0000;        // No write request
    always_comb inst_wdata = `ZERO_REG;      // No write request
    
    always_comb inst_addr = inst_sram_addr;
    always_comb inst_req = inst_sram_en;
    
    always_comb inst_addr_ok_o = inst_addr_ok_i;
    always_comb inst_data_ok_o = inst_data_ok_i;
    
endmodule
